System-Level Energy Efficiency in High-Resolution SAR ADCs: Switching, Reference Delivery, and Digital Calibration
DOI:
https://doi.org/10.54097/pe599b27Keywords:
Successive-Approximation-Register ADC, Capacitive DAC, Charge Recycling, Reference Buffer, Background Calibration, Comparator NoiseAbstract
SAR ADC is suitable for sensor interfaces with strict power consumption limitations, such as biomedical, wearable devices, and the Internet of Things, due to its dynamic working mode and low power consumption. However, when the resolution of SAR ADC is increased to 14-16 bits, the power consumption and area of CDAC will sharply increase; Simultaneously reducing the size of CDAC can cause issues such as capacitor mismatch; Sampling and comparator noise both limit its energy efficiency and accuracy. This article provides an overview of key optimization techniques in high-resolution and low-power SAR ADCs. Discuss low-energy CDAC switching and charge recovery methods from two aspects: switch energy consumption and reference transient load; Analyze the collaborative design of CDAC and reference buffer, as well as the impact of reference voltage establishment error on conversion accuracy; Finally, compare the front-end and back-end calibration methods, and discuss their convergence time and trade-off with digital circuit power consumption.
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