PAN, Qixu. Technical Bottlenecks and Process Optimization Pathways for AI Chip Wafer Manufacturing under Advanced Semiconductor Nodes. International Journal of Advanced Engineering and Technology Research, [S. l.], v. 3, n. 2, p. 76–79, 2026. DOI: 10.54097/v1tq3e15. Disponível em: https://ijaetr.org/index.php/ojs/article/view/151. Acesso em: 19 oct. 2026.